Wiring technology in which copper lines are substituted for aluminum lines have recently become popular because of needs and wants of enhanced performances of semiconductor devices. Copper has advantageous features of being lower in resistance and superior in electro-migration tolerance (EM tolerance) as compared with aluminum while having disadvantageous features of greater possibility of diffusion into semiconductor substrate and higher liability to be oxidized. In order to cope with such problems, various types of barrier materials referred to as barrier metals or protection films are formed between multi-layered wiring copper and interlayer insulating film (hereinafter referred to as “insulating film”) in the semiconductor devices.
One of methods for implementing multi-layered wiring of copper as mentioned above is damascene process, and FIGS. 9A, 9B, 9C, and 9D illustrate sequential steps of the process. Reference numeral 11 in the drawings denotes first insulating film of SiO2, and after the insulating film 11 along with concavity 12 defined to embed wiring is coated with a barrier material (barrier metal) 13 such as TaN or TiN, wiring copper (Cu) buries the concavity (see FIG. 9).
The surface of the substrate is polished by means of a polishing procedure referred to as chemical mechanical polishing (CMP) to eliminate the copper 14 and barrier metal 13 except for those in the concavity 12, and after forming protection film or silicon nitride film (referred to as SiN film hereinafter) 15 so as to close an opening of the concavity 12, second insulating film 16 is formed thereon (see FIG. 9B). The SiN film 15 is useful to prevent the copper 14 from diffusing into the second insulating film 16. With a mask (not shown), the insulating film 16 is partially etched away to define a second groove 17 (see FIG. 9C). Moreover, after the SiN film 15 in the groove 17 is etched away (see FIG. 9D), the second groove 17 is buried with copper, and these steps are repetitively carried out to implement a multi-layered configuration.
However, the SiN film 15 serving as the protective film in the above-mentioned damascene process has a high dielectric constant, and the residual SiN film remaining between the insulating films 11 and 16 disadvantageously causes the dielectric constant to be raised as a whole in the interlayer insulating film even if the interlayer insulating film is made of a material with a low dielectric constant.
Moreover, if the SiN film is used as the protection film, then etching must be conducted twice for removing the SiN film 15. More specifically, the second insulating film 16 is first etched to make a second groove 17, and thereafter, the SiN film 15 must undergo etching under different process conditions, by exchanging processing gas used in the etching, for example. The SiN film is formed through chemical vapor deposition (CVD), and this also disadvantageously leads to complicating the total manufacturing process.